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mental improvements during the same period. What is clearly needed in verification techniques and technology is the equivalent of a synthesis productivity breakthrough. In the second edition of Writing Testbenches, Bergeron raises the verification level of abstraction by introducing coverage-driven constrained-random transaction-level self-checking testbenches all made possible through the introduction of hardware verification languages (HVLs), such as e from Verisity and OpenVera from Synopsys. The state-of-art methodologies described in Writing Test benches will contribute greatly to the much-needed equivalent of a synthesis breakthrough in verification productivity. I not only highly recommend this book, but also I think it should be required reading by anyone involved in design and verification of today's ASIC, SoCs and systems. Harry Foster Chief Architect Verplex Systems, Inc. xviii Writing Testbenches: Functional Verification of HDL Models PREFACE If you survey hardware design groups, you will learn that between 60% and 80% of their effort is now dedicated to verification.
| ISBN-13 | 9781461350125 |
|---|---|
| ISBN-10 | 1461350123 |
| Weight | 1.57 Pounds |
| Dimensions | 6.10 x 1.16 x 9.25 In |
| List Price | $249.99 |
| Edition | 2nd Edition |
| Format | Paperback |
|---|---|
| Language | English |
| Pages | xxx, 478 pages |
| Publisher | Springer |
| Published On | 2012-10-21 |
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Alibris
Sparks, NV, USA
Print on demand Trade paperback (US). Glued binding. 478 p.
Free delivery by: 04 Apr 2026