Overview

Introduction to Logic Synthesis Using Verilog HDL explains how to write accurate Verilog descriptions of digital systems that can be synthesized into digital system netlists with desirable characteristics. The book contains numerous Verilog examples that begin with simple combinational networks and progress to synchronous sequential logic systems. Common pitfalls in the development of synthesizable Verilog HDL are also discussed along with methods for avoiding them. The target audience is anyone with a basic understanding of digital logic principles who wishes to learn how to model digital systems in the Verilog HDL in a manner that also allows for automatic synthesis. A wide range of readers, from hobbyists and undergraduate students to seasoned professionals, will find this a compelling and approachable work. The book provides concise coverage of the material and includes many examples, enabling readers to quickly generate high-quality synthesizable Verilog models.
ISBN-13

9783031797422

ISBN-10

3031797426

Weight

0.39 Pounds

Dimensions

7.52 x 0.24 x 9.25 In

List Price

$29.99

Edition

1st Edition

Format

Paperback

Language

English

Pages

vii, 75 pages

Publisher

Springer

Published On

2007-12-31


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Books From California
★★★★☆

Simi Valley, CA, USA

Cover and edges may have some wear. Very Clean Copy-Over 500, 000 Internet Orders Filled.
$30.48

 Free delivery by: 01 Apr 2026

Used, Very Good
Seller details
Books From California
★★★★☆

Simi Valley, CA, USA

Very Clean Copy-Over 500, 000 Internet Orders Filled.
$30.48

 Free delivery by: 01 Apr 2026


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